march 1999 1/5 AN397 application note timing specifications for memory products stmicroelectronics has, for many years, committed itself to the jedec naming convention for the timing parameters of its memory products. historically, timing parameter names had tended towards describing the function that was being performed during the time interval, for example: Ct ah to represent the address hold time Ct dh to represent the data hold time Ct acc to represent the access time however, these names are ambiguous. they do not specify which signals are used to indicate the start and end events, and they do not specify which transitions are involved. for example, t acc does not spec- ify, whether this is the time from addresses becoming valid, or from the chip enable becoming enabled, or from the chip enable ceasing to be disabled. under the jedec system, timing parameter names are composed from the names of the signals involved, and their corresponding logic transitions. they take the general form, t 1234 , where 1 and 3 specify two signal names, and 2 and 4 specify the logic transitions. each timing period consists of a start event, as specified by a given logic transition-2 on signal-1, and an end event, as specified by a given logic transi- tion-4 on signal-3. to help in keeping the names of the timing periods consistent between designers, there are conventions on how the signal names, 1 and 3, should be chosen, and on how the transition names, 2 and 4, should be specified. the core of the signal naming system is as follows: C q to represent a data output C d to represent a data input C a to represent an address line C e to represent a chip enable input C g to represent a, output enable input C w to represent a write enable input these are shown in use for the example memory device in figure 1.
AN397 - application note 2/5 figure 1. signal names on an example memory device the naming convention for the transitions is as follows: C h indicates the earliest moment at which the signal can be considered to be driven in the high logic state (for example, as a result of a low-to-high transition). C l indicates the earliest moment at which the signal can be considered to be driven in the low logic state (for example, as a result of a high-to-low transition). C v indicates the earliest moment at which the signal can be considered to be driven in a valid logic state, either high or low (for example, as a result of coming out of a high-to-low, or low-to-high transition, passing through the invalid state in between). C x indicates the earliest moment at which the signal can be considered to be driven in the invalid logic state (between v il and v ih in figure 2), neither high nor low (for example, as a result of going into a high-to-low, or low-to-high transition, passing through the invalid state in between). C z indicates earliest moment at which the signal can be considered to be undriven, and left floating in its high impedance state. figure 2. logic state transitions on example input and output waveforms ai00708b 15 a0-a14 w dq0-dq7 v pp v cc g e v ss 8 ai00830b v oh v ol transition (x) v ih v il v oh v ol valid v ih v il valid v oh v ol high low v ih v il
3/5 AN397 - application note examples the parameter t avqv specifies a time interval: starting from the instant when the address lines are below v il (for signals at, or going to a logic low level) or above v ih (for those at, or going to a high logic level); and ending at the instant when the data output signals are all below v il or above v ih . the parameter t ehqz specifies a time interval: starting from the instant when the chip enable input goes above v ih ; and ending at the instant when the data output is no longer driven. the parameter t axqx specifies a time interval: starting from the instant when any single address line goes outside its stable, valid level; and ending at the instant when any data output line transition passes these levels, and is consequently no longer valid. some further examples are shown in the first column of table 1. the second column indicates the old style of name for the same parameter. as can be seen in some of the names, the inversion bar is always omitted from signals that use negative logic. for example, e from figure 1 appears as e in t elqx in table 1. table 1. timing characteristics example notes: 1. these are taken from the flash memory data sheets. measurement conditions there are a few other parameters that need to be included in the data sheets, to make the specification complete. firstly, the limits on the output levels, as used in figure 2, need specifying: v oh 3 0.8 v cc v ol 0.2 v cc next, the thresholds recognized by the input buffers, again as used in figure 2, need specifying: v ih 3 0.7 v cc v il 0.3 v cc finally, the reference voltages for the timing measurements need specifying. let us call them v rh and v rl , here, but note that, because these are not physical parameters of the hardware, they are not gener- ally given explicit names in the data sheet. however, they do appear in the ac measurement conditions table, and in the accompanying ac testing input output waveforms diagram. generally, they set at v ih (min) and v il (max), respectively. that is, the measurement equipment is set to recognize the logic thresholds at the same voltages as are recognized by the input buffers of the chip. v rh = 0.7 v cc v rl = 0.3 v cc symbol alt. parameter t avav t rc read cycle time t avqv t acc address valid to output valid t elqx t lz chip enable low to output transition t elqv t ce chip enable low to output valid t glqx t olz output enable low to output transition t glqv t oe output enable low to output valid t ehqz chip enable high to output hi-z t ghqz t df output enable high to output hi-z t axqx t oh address transition to output transition
AN397 - application note 4/5 notice, though, that this is by definition, and is not itself a measured parameter (hence the equal sign, rather than the less than or equals or greater than or equals sign for the bounded value. although, in theory, no timings depend on the rise and fall times of signals, some products may have char- acteristics which vary with the slew rate of the input. for an st eprom device, the data sheet might state input rise and fall times are 20 ns (max). as a further point of definition, the data sheets might state that a signal is defined as hi-z (high imped- ance) when it is not driving or being driven. timing diagrams the jedec convention leads to clearer, less ambiguous timing specifications. also, it allows a substantial simplification to be made to timing diagrams, and hence to an increase in their clarity. since the voltage reference levels (v rh and v rl ) are specified explicitly in the data sheet, as described in the section above, these levels do not need to be spelled out precisely each time on the timing diagram. instead, it is sufficient to depict, diagrammatically, the timing events starting and ending at the midpoints of logic transitions, and to let the name of the parameter indicate which of the reference levels are involved. for example, the data sheet might specify the measurement conditions, with v cc =5 v, as follows: C input voltage levels are v ol =1 v and v oh =4 v C input and output timing reference levels are 1.5 v and 3.5 v C output hi-z is the point where the signal is no longer driving the parameters in the timing diagram (figure 3) would then be interpreted as follows: Ct avav is measured from the point where all address lines are either above 3.5 v or below 1.5 v, to the point of similar conditions at the end of the cycle. Ct elqv is measured from e being below 1.5 v, to the point when all data lines are either above 3.5 v or below 1.5 v. Ct ehqz is measured from e being above 3.5 v, to the point when the data outputs are no longer driving the signal lines. note that, in figure 3, the t elqv timing, for example, is shown diagrammatically not from a low point on the e falling edge, but from the center, and is shown not to a high/low point on the data output but again to the center. figure 3. timing diagram (an example) ai00709 tehqz data out a0-a14 e dq0-dq7 tavav telqv valid
5/5 AN397 - application note if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1999 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com
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